1. Technical Field
The present invention relates to a semiconductor memory apparatus, and in particular to a semiconductor memory apparatus which enhance the drivability of a sense amplifier driver during a refresh operation.
2. Related Art
In general, a memory cell of a dynamic random access memory (DRAM) is composed of one transistor and one capacitor. A sensing operation is carried out by selecting the memory cell with a word line coupled to a gate terminal of the transistor, and amplifying a voltage applied to the source terminal of the transistor by the capacitor coupled to the drain terminal of the transistor. During this operation, DRAM conducts an over-drive operation to charge a selected bit line up to a target level by sensing a memory cell more quickly. Namely, when the voltage of a bit line is changed to a core voltage level, an external power source voltage is supplied to the bit line to make the voltage of the bit line rapidly rise up to the core voltage level.
The bit-line sensing operation in DRAM is also carried out in a refresh mode, in addition to normal input/output modes. However, in the refresh mode, the external power source voltage to the bit line is interrupted, reducing current dissipation.
FIG. 1 is a block diagram of a semiconductor memory apparatus according to the conventional art.
The semiconductor memory apparatus shown in FIG. 1 includes a power supply controlling unit 10 that selectively outputs a first power control signal VSC_1 or a second power control signal VSC_2 in response to a refresh signal REF for determining a refresh operation and an active signal ACT that determines a bit-line sensing operation by a sense amplifier; a power supply unit 20 that selectively outputs an external power source voltage VDD or a core voltage Vcore in response to the first power control signal VSC_1 or the second power control signal VSC_2; a sense-amp driver 30 that supplies the sense amplifier with the external power source voltage VDD or the core voltage Vcore provided by the power supply circuit 20; and a core voltage generator 40 that generates the core voltage Vcore using the external power source voltage VDD.
When the semiconductor memory apparatus is not in the refresh mode, the refresh signal REF is disabled. During this time, if the active signal ACT becomes enabled, the first power control signal VSC_1 is output from the power supply controlling unit 10, and is enabled for a predetermined time. Then, after the predetermined time, the first power control signal VSC_1 is disabled and the second power control signal VSC_2 is enabled. When the active signal ACT is disabled, the second power control signal VSC_2 is disabled.
On the contrary, when the semiconductor memory apparatus is in the refresh mode, the refresh signal is enabled. During this time, if the active signal ACT is enabled, the second power control signal VSC_2 is output from the power supply controlling unit 10, and is enabled for a predetermined time. Thereafter, if the active signal ACT is disabled, the second power control signal VSC_2 is disabled.
The power supply unit 20 supplies the external power source voltage VDD to the sense-amp driver 30 when the first power control signal VSC_1 is enabled, while it supplies the core voltage Vcore to the sense-amp driver 30 when the second power control signal VSC_2 is enabled.
The sense-amp driver 30 supplies the sense amplifier with the external power source voltage VDD or the core voltage Vcore.
On the other hand, the core voltage Vcore generated by the core voltage generator 40 is a voltage used as a power source voltage in a core circuit region of the semiconductor memory apparatus.
As such, in the conventional art, during an active operation in the normal mode of the semiconductor memory apparatus, the over-drive function is enabled to supply the external power source voltage VDD to the sense-amp driver 30 to efficiently sense a bit line. During an active operation in the refresh mode of the semiconductor memory apparatus, the core voltage Vcore is supplied to the sense-amp driver 30 without enabling the over-drive operation to reduce power consumption. However, since the core voltage Vcore is used in a plurality of memory banks, the drivability of the bit-line sensing is degraded so a selected bit line hardly reaches the level of the core voltage Vcore in a predetermined time, resulting in a malfunction in sensing the selected bit line.